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Lattice Semiconductor
Turbo Decoder User’s Guide
Lattice provides a Turbo Decoder IP core that is both ?exible and compliant with three different standards: 3GPP,
3GPP2 and CCSDS. 3GPP is widely used in WCDMA and MC-CDMA applications while CCSDS is most com-
monly found in telemetry and space communications. Figure 1 shows the top-level block diagram of this core.
Lattice also supplies a Turbo Encoder core that provides a complete state-of-the-art error correction solution.
Figure 1. Turbo Decoder I/O Block Diagram
rstn
sr
din
inpvalid
rfi
dout
rfno
rfo
Turbo
Decoder
blocksizeset(ipcfgset)
blocksize
iterations
clk
rate
Note: Additional I/O signals are required if either an external memory or double buffer is selected. Please refer to
the Additional Signals for External Memory section of this document for further information.
MAP Algorithm
Turbo decoding is based on the principle of comparing the probability of a received soft input data being a ‘1’ and
‘0’. The Lattice Turbo Decoder uses a decoding scheme called the MAP - Maximum Aposteriori Probability algo-
rithm. The algorithm determines the probability of whether each received data symbol is a ‘1’ as well as ‘0’. This is
done with the help of the data, parity symbols, and the decoder knowledge of the encoder trellis. A trellis is a form
of a state transition table of the encoder input/output. Based on the data and parity information, the MAP decoder
computes the probability of the encoder being in a particular state. Depending on the soft data, parity value and the
weight from the previous state, the probability that the data is a ‘1’ or ‘0’ can be computed. The MAP decoder com-
putes the weight for each data symbol in a given block for both the forward and reverse direction. This results in the
computation of a forward and reverse metric. Using these two values, the probabilities are computed. After the
probabilities are determined, they are compared and a decision is made. The Lattice Turbo Decoder IP core uses
the logarithm of the probability to reduce computation; this is known as Log Likelihood ratio (LLR). The computation
of the probabilities is done iteratively to obtain a reliable result. Once the result is considered reliable, one can
make a ?nal decision as to whether the data symbol is a ‘1’ or a ‘0’. The Lattice Turbo Decoder can implement both
the Log-Map and Max-Log-Map algorithm. The Log-Map algorithm gives a slightly better performance than the
Max-Log-Map but utilizes more resources and runs at a slower frequency.
The Log Likelihood ratio is the probability that the received data bit is a ‘0’ divided by the probability that the
received data bit is a ‘1’.
L(D) = log
P (D=0)
P (D=1)
The value of L(D) is positive if P(D=1) ≤ P(D=) and negative otherwise. The output data value is ‘1’ if L(D) is positive
and ‘0’ if L(D) is negative. For one complete cycle of iteration, one needs to compute the LLR using parity for non-
interleaved as well as interleaved data.
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